About

I am a Master’s student in Integrated Circuit Design at TUM Asia and Nanyang Technological University, with experience in both analog/mixed-signal and digital IC design.

In analog and mixed-signal design, I have worked on transistor-level circuits including amplifiers, charge pumps, and bandgap-based references, with full-custom layout and post-layout verification.

In digital design, I have developed an RTL RISC-V CPU with differential testing and system-level bring-up, building a structured approach to design, verification, and integration.

Technical Skills

Digital & RTL

  • Verilog, RISC-V CPU Design
  • Datapath and Control Logic
  • Basic Verification and Debugging (Verilator, Waveform Analysis)
  • Python for test automation and tooling, Makefile for build flow

Analog / Mixed-Signal IC

  • Cadence Virtuoso (schematic & full-custom layout), Spectre simulation
  • DRC / LVS / PEX, post-layout verification and PVT analysis
  • Analog building blocks: amplifiers, charge pumps, bandgap-based references
  • Device sizing, bias design, stability and trade-off analysis

Embedded & Systems

  • C/C++, MCU Development
  • Sensor Integration and Motor Control
  • System-Level Debugging

Additional

  • PCB Design (Altium Designer)
  • CST (RF Simulation)
  • 3D Modeling and 3D Printing

Education

  • M.Sc. Integrated Circuit Design, TUM Asia & NTU (2025–2027)
  • B.Eng. Electronic Information Engineering, JSNU