Projects

IC Projects

RTL RISC-V CPU Implementation & Verification

Designed and verified a multi-cycle RTL RISC-V CPU with latency-insensitive handshake-based microarchitecture, differential testing, and RTOS bring-up.

• Designed a modular multi-cycle RV32E CPU (IF/ID/EX/LSU/WB) with valid-ready handshake for stage and memory interaction
• Implemented machine-mode privilege architecture including CSR subsystem and precise exception/trap handling
• Built a C reference model (RV32E + M) and developed differential testing (DUT vs. reference) for instruction-level verification
• Integrated a custom SimpleBus-based memory interface with request/response protocol supporting variable-latency access
• Designed and integrated an AXI4-Lite read interface for instruction-fetch memory access, enabling bus-based external memory communication
• Developed a Verilator-based simulation framework with waveform tracing, instruction/memory trace, and debug tooling
• Successfully booted RT-Thread RTOS on the RTL CPU, validating system-level execution and exception handling

Tools: Verilog, C/C++, Python, Verilator, GTKWave, RISC-V ISA, Difftest

Class-AB Audio Amplifier Design in GF 0.18-μm CMOS

Designed a class-AB audio amplifier with full-custom layout and post-layout verification.

• Designed amplifier, bias, and start-up circuits
• Applied translinear-loop class-AB control and Ahuja compensation
• Completed layout with DRC/LVS clean and PEX
• Verified performance across PVT corners
• Achieved ~12-dB gain, ~300-kHz UGBW, >60° phase margin

Tools: Cadence Virtuoso, Spectre, Layout, DRC, LVS, PEX

Digitally Controlled Cross-Coupled Charge Pump in 0.18-µm CMOS

Designed a 2-stage cross-coupled charge pump with 4-phase non-overlapping clock generation and closed-loop digital regulation in Cadence Virtuoso.

• Designed a 2-stage cross-coupled charge pump for on-chip voltage boosting
• Implemented 4-phase non-overlapping clock generation to improve charge transfer stability
• Optimized device sizing and pumping capacitance to balance boosting capability, ripple, and startup behavior under leakage effects
• Built a bang-bang closed-loop digital control scheme using comparator feedback for output regulation
• Achieved regulated output of 2.94-3.01 V from a 1.8 V supply with about 70 mV peak-to-peak ripple under ~100 kΩ load in schematic-level simulations

Tools: Cadence Virtuoso

Bandgap-Based Reference Voltage Design in TSMC 0.18-μm CMOS

Designed a temperature-compensated reference circuit based on BJT ΔVbe generation and PTAT/CTAT compensation.

• Implemented ΔVbe generation using BJT area ratio (N = 4)
• Designed bias network and current mirrors for stable operation
• Optimized resistor ratios to balance PTAT and CTAT components
• Achieved ~25 ppm/°C over -40°C to 100°C
• Output reference voltage ~2.54 V

Tools: Cadence Virtuoso, Spectre