
Digital IC · RTL · SoC
Multi-Cycle RISC-V CPU / SoC
RV32E CPU RTL, valid-ready control, AXI/APB integration, NEMU Difftest, memory models, and bootloader debug.
Project details →2027 · IC Design
TUM / NTU · M.Sc. Integrated Circuit Design · Expected graduation: 2027
Infineon Technologies Singapore · Mixed-Signal Design Engineer
Analog / Mixed-Signal IC · Digital IC / RTL · SoC Design

Digital IC · RTL · SoC
RV32E CPU RTL, valid-ready control, AXI/APB integration, NEMU Difftest, memory models, and bootloader debug.
Project details →

Analog IC · Layout · PEX
GF 0.18 µm transistor-level design, full-custom layout, DRC/LVS/PEX, post-layout and process-corner simulation.
Project details →Embedded · PCB · System Bring-Up
Our team won second prize at the national finals. I worked on the boards, inter-vehicle communication, control tuning, and vehicle integration.
TI Cup · Jiangsu First Prize
Built around the MSP430F5529, the two cars follow a track and maintain their spacing using line sensors, ultrasonic ranging, and Bluetooth communication.
View certificate ↗
RF · CST · PCB Measurement
I designed, built, and measured a compact RF filter. This work led to a first-author paper in Micromachines.
Project details →Experience
Mixed-Signal Design Engineer · 2026.06–2027.04
Currently working on an energy-harvesting chip that can start up and operate at an input voltage of 0.1 V.
Experience details →More Engineering Work
Introductory coursework · Synthesis · Place and route
TSMC 0.18 µm · Schematic · Temperature Sweep
Publications & Patent
Ultra-Compact Low-Pass Spoof Surface Plasmon Polariton Filter Based on Interdigital Structure
Publications →Awards
Also awarded a Jiangsu TI Cup First Prize and a Jiangsu Division Electronic Design Contest Second Prize.
All awards →Education
M.Sc. Integrated Circuit Design
B.Eng. Electronic Information Engineering